Embedded DRAMs (eDRAMs) with wide data bandwidth and wide internal bus width have been proposed to be used as L2 (level-2) cache to replace pure SRAM cache. Since each DRAM memory cell is formed by a transistor and a capacitor, the size of DRAM cache is significantly smaller than that of SRAM cache. In order to meet performance requirements, DRAMs are made of a plurality of blocks or micro-cells. A block is a small DRAM array unit formed by a plurality of wordlines (e.g., from 64 to 256) and a plurality of bitline pairs (e.g., from 64 to 256). The size of a block is much smaller (e.g., 16× to 256×) than that of a bank of a conventional stand-alone DRAM. Only one block of the eDRAMs is activated each time. The read and write speed of an eDRAM can be fast due to very light loading of wordlines and bitlines.
In order to effectively utilize the large DRAM cache size, many SRAM macros are required to facilitate a high-speed pipeline operation in an eDRAM system. A first SRAM macro is required as a cache interface to be placed between the mass eDRAM arrays and the processor(s). The first SRAM macro is about the same size of an eDRAM block. Hence, area penalty is minimal.
The wide internal bus is used for facilitating a high data transfer rate among eDRAM, SRAM, and the processor(s). More specifically, data residing in eDRAM memory cells coupled to a wordline traversing an eDRAM block is transferred to primary sense amplifiers. The data is then transferred to corresponding secondary sense amplifiers. The data is then transferred to the first SRAM macro, i.e., the SRAM cache, and stored in the memory cells thereof at the same wordline location.
A second SRAM macro, called TAG block cache, is used to record the addresses of those micro-cells whose data are temporarily stored within the SRAM cache. The data is then transferred to the processor(s). When an incoming address is issued, the TAG block cache is examined to determine whether it is a hit or a miss. A hit means data are currently stored in the SRAM cache and can be retrieved immediately. A miss, on the other hand, means data must be retrieved from the DRAM.
A third SRAM macro is used to record redundancy information, including failed row and column addresses of the DRAM arrays. Therefore, whenever accessing a DRAM array, the redundancy information is provided so that the defective row and/or column is replaced with the good redundant elements.
A fourth SRAM macro can be used for BIST operation. For example, the addresses of defective column or row elements must be temporarily recorded during a test mode. At the end of the test mode, when the redundancy algorithm is satisfied, the recorded addresses are used to program the fuses.
Finally, another SRAM macro may be required to store a portion of a test program for executing the test mode. Generally, there are two sets of test programs. The first set of programs are those fixed programs used to test the memory. This set is typically stored in a ROM. The second set of programs are those programmable programs used to test customized memory, or to provide test flexibility. This set is stored in SROM (scannable ROM). Similar to a fuse register array, the SROM is not an area efficiency design. The SROM can be replaced with an SRAM macro.
An eDRAM system having several small SRAM macros is not area efficient. Since each small SRAM macro contains about a 50% area for support circuits, e.g., sense amplifiers, decoders and drivers. Accordingly, a need exists for a unified SRAM cache system incorporating the several SRAM macros of an eDRAM system and their functions, so that each incorporated SRAM macro can be independently accessed without interfering with the other incorporated SRAM macros within the unified SRAM cache system. A need also exists for a unified SRAM cache system, as described in the previous sentence, where the incorporated SRAM macros share a single set of support circuits without compromising the performance of the eDRAM system.